dc.contributor.author | Chen, Yu-Hsin | |
dc.contributor.author | Krishna, Tushar | |
dc.contributor.author | Emer, Joel S. | |
dc.contributor.author | Sze, Vivienne | |
dc.date.accessioned | 2016-02-10T20:59:22Z | |
dc.date.available | 2016-02-10T20:59:22Z | |
dc.date.issued | 2016-02 | |
dc.identifier.isbn | 978-1-4673-9467-3 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/101151 | |
dc.description.abstract | Deep learning using convolutional neural networks (CNN) gives state-of-the-art
accuracy on many computer vision tasks (e.g. object detection, recognition,
segmentation). Convolutions account for over 90% of the processing in CNNs
for both inference/testing and training, and fully convolutional networks are
increasingly being used. To achieve state-of-the-art accuracy requires CNNs with
not only a larger number of layers, but also millions of filters weights, and varying
shapes (i.e. filter sizes, number of filters, number of channels) as shown in Fig.
14.5.1. For instance, AlexNet [1] uses 2.3 million weights (4.6MB of storage) and
requires 666 million MACs per 227×227 image (13kMACs/pixel). VGG16 [2] uses
14.7 million weights (29.4MB of storage) and requires 15.3 billion MACs per
224×224 image (306kMACs/pixel). The large number of filter weights and
channels results in substantial data movement, which consumes significant
energy. | en_US |
dc.description.sponsorship | United States. Defense Advanced Research Projects Agency (DARPA YFA grant N66001-14-1-4039) | en_US |
dc.description.sponsorship | Intel Corporation | en_US |
dc.description.sponsorship | Massachusetts Institute of Technology. Center for Integrated Circuits and Systems | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | https://submissions.mirasmart.com/isscc2016/PDF/ISSCC2016AdvanceProgram.pdf | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Sze | en_US |
dc.title | Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Chen, Yu-Hsin, Tushar Krishna, Joel Emer, and Vivienne Sze. "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks." in ISSCC 2016, IEEE International Solid-State Circuits Conference, Jan. 31-Feb. 4, 2016. San Francisco, CA. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Sze, Vivienne | en_US |
dc.contributor.mitauthor | Chen, Yu-Hsin | en_US |
dc.contributor.mitauthor | Krishna, Tushar | en_US |
dc.contributor.mitauthor | Emer, Joel S. | en_US |
dc.contributor.mitauthor | Sze, Vivienne | en_US |
dc.relation.journal | IEEE International Conference on Solid-State Circuits (ISSCC 2016) | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dspace.orderedauthors | Chen, Yu-Hsin; Krishna, Tushar; Emer, Joel; Sze, Vivienne | en_US |
dc.identifier.orcid | https://orcid.org/0000-0002-3459-5466 | |
dc.identifier.orcid | https://orcid.org/0000-0002-4403-956X | |
dc.identifier.orcid | https://orcid.org/0000-0003-4841-3990 | |
mit.license | OPEN_ACCESS_POLICY | en_US |